*Problem:
Was not able to use more than 16MB since chipset was caching only
the first 16MB.  No option in the X-Setup to change this.  20MB
is available, but the performance penalty is too severe unless all
20MB can be cached.

*Hardware:
i486DX/100 CPU, 256KB L2, 20MB DRAM, 4x4MB plus 4x1MB (okay so far),
VEGA motherboard with Symphony Haydn chipset (problem).

*Fix:
XMTP results before running the two programs (listed below) is first,
followed by, XMTP results after each program is run.  Note the non-cached
region at 16MB+.  Unfortunately, my AMI X-BIOS setup does not offer any
sort of control over the region to cache, though it is part of the chipset.
Even AMISETUP, an AMI BIOS setup extension program, does not offer any
such control (apparently it's limited to what is actually available in
the X-BIOS setup).
 
Three XMTP read-performance snap-shots follow.  The write tests for
all three runs were then same, with a 23us/KB result (over the entire
range, even in the BEFORE run, and without running SYM32MB.COM --
this is because the write-through cache has a buffer -- also settable
from software via the chipset I/O -- not a write-back cache, a buffered
write-through (sounds awfully alike, though, ey?)).

The test program is available at SimTel mirrors, in sysutil/ as xmtp11.zip.
It uses block sizes from 1K to 1MB in size and tests how fast it can
perform a LODSD (a 3-clock per dword operation) or STOSD (write test).
An alternate test is also available.

----BEFORE----
Note the break at 1000000 (16MB mark).  This causes major slow-downs
in OS/2 since the OS/2 kernel is loaded high and runs out of this
(slow) memory.  Expect similar results in NT, and probably Win9x.

Extended Memory Read: 19MB +  0KB using REP LODSD
   MB    1   2   4   8   16  32  64 128 256 512 1024 BlkSz
0000000  -   -   -   -   -   -   -   -   -   -   -  (n/a)
0100000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0200000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0300000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0400000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0500000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0600000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0700000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0800000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0900000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0A00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0B00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0C00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0D00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0E00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0F00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
1000000  54  54  54  55  55  54  55  55  54  54  ov uS/KB
1100000  54  54  54  54  54  55  54  54  55  54  ov uS/KB
1200000  55  55  54  55  55  55  55  54  55  54  ov uS/KB
1300000  54  54  54  55  55  55  54  54  55  54  ov uS/KB

Extended Memory Write: 19MB +  0KB using REP STOSD
   MB    1   2   4   8   16  32  64 128 256 512 1024 BlkSz
0000000  -   -   -   -   -   -   -   -   -   -   -  (n/a)
0100000  25  23  23  23  23  23  23  23  23  23  23 uS/KB
         :  (all writes test gave exact same results)
1300000  23  23  23  23  23  23  23  23  23  23  23 uS/KB


----AFTER SYM32MB.COM----
Note that there's no more break.  Great for OS/2, only
the BIOS resets the chipset so that only 16MB is cached
upon a reset, even a warm boot.  This means I need to
write an OS/2 program to do this.  If interested, contact
me and I'll let you have it (once I do it).

Extended Memory Read: 19MB +  0KB using REP LODSD
   MB    1   2   4   8   16  32  64 128 256 512 1024 BlkSz
0000000  -   -   -   -   -   -   -   -   -   -   -  (n/a)
0100000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0200000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0300000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0400000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0500000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0600000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0700000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0800000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0900000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0A00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0B00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0C00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0D00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0E00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
0F00000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
1000000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
1100000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
1200000  10  10  10  10  10  19  19  19  19  45  45 uS/KB
1300000  10  10  10  10  10  19  19  19  19  45  45 uS/KB


----AFTER SYMBURST----
My BIOS defaults the cache burst to disabled.  Hm.  I can
option this to either a 2-clock burst or a 4-clock burst.
Since the 2-clock setting locks up, I use 4-clock.  No
problems so far.  Note how the 512K and 1MB block size
results improve a good 30%.

Extended Memory Read: 19MB +  0KB using REP LODSD
   MB    1   2   4   8   16  32  64 128 256 512 1024 BlkSz
0000000  -   -   -   -   -   -   -   -   -   -   -  (n/a)
0100000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0200000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0300000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0400000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0500000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0600000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0700000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0800000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0900000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0A00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0B00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0C00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0D00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0E00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
0F00000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
1000000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
1100000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
1200000  10  10  10  10  10  19  19  19  19  33  33 uS/KB
1300000  10  10  10  10  10  19  19  19  19  33  33 uS/KB

Debug listings follow.  It's all I have now, and probably
all I'll post.  Interested types (VEGA motherboard and
Symphony chipset owners) should e-mail me for more stuff,
especially the OS/2 version.

SYM32.COM                      SYMBURST.COM
Sets cache range to 32MB.      Sets cache burst to 4-clock mode.
0100 MOV AL,45                 0100 MOV AL,40
0102 OUT A8,AL                 0102 OUT A8,AL
0104 NOP                       0104 NOP
0105 IN  AL,A9                 0105 IN  AL,A9
0107 AND AL,F8                 0107 AND AL,08
0109 OR  AL,03                 0109 OR  AL,80
010B OUT A9,AL                 010B OUT A9,AL
010D INT 20                    010D INT 20

This information was gathered from the c't magazine FTP site.  The
archive CHIPS.ZIP contains about a dozen or so chipset documents,
and a program to run to check your current settings.  Came across
it while looking for another program (thanks guy).  BTW, the site
is in Germany: (site here).
